Phase locked loops receive an input signal and respond by producing an output signal of substantially the same frequency with a predetermined phase relation to the input signal. The output signal may, for example, be used as the basis for sampling a data signal wherein matching of frequency and establishing a given phase relation with the data signal are essential to accurate information recovery.
An important characteristic of a phase locked loop is the maximum lock time, i.e., the maximum time required to establish the desired frequency and phase relation. Average lock time is an important measure of circuit performance, but maximum lock time must be considered in allocation of time permitted for phase acquisition. More particularly, a phase locked loop circuit must be allowed at least its maximum lock time before the output can be considered valid.
Phase locked loop circuits suffer from "hang-up", a condition where the circuit dwells about a reverse null point, an unstable equilibrium point having a large phase error. The source of hang-up is generally attributed to the small correcting voltage produced by the phase detector in the vicinity of the reverse null and by equivocation about the reverse null caused by signal noise. If the initial phase error is close to the reverse null point, then hang-up is likely and phase acquisition is delayed. The maximum lock time for a circuit susceptible to hang-up must account for the possibility of delay caused by hang-up. Thus, circuits susceptible to hang-up have greater maximum lock time and must be allocated greater time for phase acquisition.
Fast phase acquisition is essential in, for example, burst mode signal communication systems where rapid phase acquisition promotes efficient channel time usage and, for battery operated devices, reduces battery consumption. Typically a phase locked loop must establish a phase relation with the data signal during a short synchronization preamble preceding a data burst. Failure of the phase locked loop to quickly establish phase acquisition results in loss of the data burst. If a phase locked loop circuit has a large maximum lock time, e.g., due to the possibility of occasional hang-up, the circuit must be given a correspondingly large time interval for phase acquisition. To conserve battery life, however, fast phase acquisition may be required to reduce overall receiver activation time. In many communication systems, therefore, a large phase acquisition interval is unacceptable.
Quick locking phase locked loops are known. These circuits generally employ additional components, typically at least two multipliers or phase detectors in a more complex circuit, to avoid hang-up and achieve rapid phase acquisition. Thus, while fast locking phase locked loops are available, they come at the cost of increased number of phase detectors and circuit complexity.
A phase locked loop circuit having reduced maximum lock time is useful because the phase locked loop output may be more quickly regarded as valid. It would be desirable, therefore, to provide a phase locked loop circuit with a single phase detector, not vulnerable to hang-up, and having limited maximum lock time.